High-performance, Low-power AVR 8-bit Microcontroller Advanced RISC Architecture 131 Powerful Instructions – Most Single Clock Cycle Execution 32 x 8 General Purpose Working Registers Up to 6 MIPS Throughput at 16MHz Fully Static Operation On-chip 2-cycle Multiplier Nonvolatile Program and Data Memories 16k Bytes of In-System Self-Programmable Flash Optional Boot Code Section with Independent Lock Bits 512K Bytes EEPROM Programming Lock for Software Security JTAG (IEEE std. 1149.1 Compliant) Interface Boundary-scan Capabilities According to the JTAG Standard Extensive On-chip Debug Support Programming of Flash, EEPROM, Fuses, and Lock Bits through the JAGS Interface